1. general description the 74hc1g125-q100; 74hct1g125-q100 is a single buffer/line driver with 3-state output. inputs include clamp diodes. this enables the use of current limiting resistors to interface inputs to vo ltages in excess of v cc . this product has been qualified to the automotive electronics council (aec) standard q100 (grade 1) and is suitable for use in automotive applications. 2. features and benefits ? automotive product qualif ication in accordance with aec-q100 (grade 1) ? specified from ? 40 ? c to +85 ? c and from ? 40 ? c to +125 ? c ? input levels: ? for 74hc1g125-q100: cmos level ? for 74hct1g125-q100: ttl level ? symmetrical output impedance ? high noise immunity ? low power consumption ? balanced propagation delays ? esd protection: ? mil-std-883, method 3015 exceeds 2000 v ? hbm jesd22-a114f exceeds 2000 v ? mm jesd22-a115-a exceeds 200 v (c = 200 pf, r = 0 ? ) 3. ordering information 74hc1g125-q100; 74hct1g125-q100 bus buffer/line driver; 3-state rev. 1 ? 18 june 2013 product data sheet table 1. ordering information type number package temperature range name description version 74hc1g125gw-q100 ? 40 ? c to +125 ? c tssop5 plastic thin shrink small outline package; 5 leads; body width 1.25 mm sot353-1 74hct1g125gw-q100 74HC1G125GV-Q100 ? 40 ? c to +125 ? c sc-74a plastic surface mounted package; 5 leads sot753 74hct1g125gv-q100
74hc_hct1g125_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserve d. product data sheet rev. 1 ? 18 june 2013 2 of 16 nxp semiconductors 74hc1g125-q100; 74hct1g125-q100 bus buffer/line driver; 3-state 4. marking [1] the pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. functional diagram 6. pinning information 6.1 pinning table 2. marking type number marking code [1] 74hc1g125gw-q100 hm 74hct1g125gw-q100 tm 74HC1G125GV-Q100 h25 74hct1g125gv-q100 t25 fig 1. logic symbol fig 2. iec logic symbol mna118 ay 2 1 4 oe mna119 1 4 2 en fig 3. logic diagram mna120 a y oe fig 4. pin configuration + & |